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10-bit, 170/200/250 msps 1.8 v a/d converter preliminary technical data ad9211 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2006 analog devices, inc. all rights reserved. features snr = 60 dbfs @ f in up to 70 mhz @ 250 msps enob of 9.7 @ f in up to 70 mhz @ 250 msps (C0.5 dbfs) sfdr = 80 dbc@ f in up to 70 mhz @ 250 msps (C0.5 dbfs) excellent linearity dnl = 0.3 lsb (typical) inl = 0.5 lsb (typical) lvds at 250 msps (ansi-644 levels) 900 mhz full power analog bandwidth on-chip reference and track-and-hold power dissipation = 380 mw typical @ 250 msps 1.25 v input voltage range 1.8 v analog supply operation output data format option data clock output provided clock duty cycle stabilizer applications wireless and wired broadband communications cable reverse path communications test equipment radar and satellite subsystems power amplifier linearization product description the ad9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. the product operates up to a 250 msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary functions, including a track-and-hold (t/h) and voltage reference, are included on the chip to provide a complete signal conversion solution. the adc requires a 1.8 v analog voltage supply and a differential clock for full performance operation. the digital outputs are lvds (ansi-644) compatible and support either twos complement, offset binary format or gray code. a data clock output is available for proper output data timing. 10 output staging - lvds d9-d0 (d4-d0 ddr mode) dco- dco+ avdd (1.8v) drvdd (1.8v) otr+ 10 ref adc 10-bit core t/h clock mgmt clk+ clk- sclk csb dgnd (pin 0) agnd vin+ vin- sdio serial port otr- reset ad9211 figure 1. functional block diagram fabricated on an advanced cmos process, the ad9211 is available in a 56-lead chip scale package (56 lfcsp) specified over the industrial temperature range (C40c to +85c). product highlights 1. high performancemaintains 60 db snr @ 250 msps with a 65 mhz input. 2. low powerconsumes only 380mw @ 250 msps. 3. ease of uselvds output data and output clock signal allow interface to current fpga technology. the on-chip reference and sample/hold provide flexibility in system design. use of a single 1.8 v supply simplifies system power supply design. supported ddr mode reduces number of output data traces 4. serial port control - standard serial port interface supports various product fu nctions such as data formatting, enabling a clock duty cycle stabilizer, power down, gain adjust and output test pattern generation. 5. pin compatible family C 12-bit pin compatible family offered as ad9230.
ad9211 preliminary technical data rev. pra | page 2 of 21 table of contents ad9211Cspecifications.................................................................... 3 ac specifications.............................................................................. 4 digital specifications........................................................................ 5 switching specifications .................................................................. 6 absolute maximum ratings 1 .......................................................... 7 esd caution.................................................................................. 7 pin configurations and function descriptions ........................... 8 terminology .................................................................................... 10 equivalent circuits .......................................................................... 12 typical performance characteristics ............................... 13 theory of operation .................................................................. 14 analog input and reference overview ................................... 14 clock input considerations ...................................................... 15 power dissipation and power down mode .................... 16 digital outputs ........................................................................... 17 timing ......................................................................................... 17 rbias........................................................................................... 18 ad9211 configuration using the spi ..................................... 18 hardware interface..................................................................... 19 reading the memory map table.............................................. 19 open locations .......................................................................... 19 default values ............................................................................. 19 logic levels................................................................................. 19 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21
preliminary technical data ad9211 rev. pra | page 3 of 21 ad9211Cspecifications table 1. dc specifications (avdd = 1.8 v, drvdd = 1.8 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.25 v, dcs enabled, unless otherwise noted.) ad9211-170/-200 ad9211-250 parameter temp min typ max min typ max unit resolution 10 10 bits accuracy no missing codes full guaranteed guaranteed offset error 25c tbd tbd mv gain error 25c tbd tbd % fs differential nonlinearity (dnl) 25c 0.3 0.3 lsb full 0.3 0.3 lsb integral nonlinearity (inl) 25c 0.5 0.5 lsb full 0.5 0.5 lsb temperature drift offset error full tbd tbd v/c gain error full tbd tbd %/c analog inputs (vin+, vinC) differential input voltage range full 1.25 1.25 v input common-mode voltage full 1.3 1.3 v input resistance (differential) full 4 4 k input capacitance 25c 2 2 pf power supply (lvds mode) avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply currents i analog (avdd = 1.8 v) 1 full 122/138 151 ma i digital (drvdd = 1.8 v) 3 full 50/50 60 ma power dissipation 3 full 310/340 380 mw power supply rejection 25c tbd tbd mv/v 1 i avdd and i drvdd are measured with a dc input at rated clock rate. see typical performance characteristics and applic ations sections for i analog and i drvdd with dynamic input vs clock rate
ad9211 preliminary technical data rev. pra | page 4 of 21 ac specifications 1 table 2. (avdd = 1.8 v, drvdd = 1.8 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.25 v, ain = -0.5dbfs, dcs enabled unless otherwise noted.) ad9211-170/-200 ad9211-250 parameter temp min typ max min typ max unit snr f in =10 mhz 25c 60 60 db full 60 60 db f in =70 mhz 25c 60 60 db full 60 60 db f in =100 mhz 25c 59 59 db f in =240 mhz 25c 58 58 db sinad f in =10 mhz 25c 60 60 db full 59.5 59.5 db f in =70 mhz 25c 60 60 db full 59.5 59.5 db f in =100 mhz 25c 58.5 58.5 db f in =240 mhz 25c 57.5 57.5 db effective number of bits (enob) f in =10 mhz 25c 9.6 9.6 bits full 9.6 9.6 bits f in =70 mhz 25c 9.6 9.6 bits full 9.6 9.6 bits f in =100 mhz 25c 9.4 9.4 bits f in =240 mhz 25c 9.2 9.2 bits worst harmonic (2nd or 3rd) f in =10 mhz 25c C80 C80 dbc full C80 C80 dbc f in =70 mhz 25c C80 C80 dbc full C80 C80 dbc f in =100 mhz 25c C78 C77 dbc f in =240 mhz 25c C75 C75 dbc worst harmonic (4 th or higher) f in =10 mhz 25c C85 C85 dbc full C85 C85 dbc f in =70 mhz 25c C85 C85 dbc full C85 C85 dbc f in =100 mhz 25c C83 C83 dbc f in =240 mhz 25c C78 C78 dbc two-tone imd 2 f1, f2 @ C7 dbfs 25c C75 C75 dbc analog input bandwidth 25c 900 900 mhz 1 all ac specifications tested by driving clk+ and clkC differentially. 2 f1 = 28.3 mhz, f2 = 29.3 mhz.
preliminary technical data ad9211 rev. pra | page 5 of 21 digital specifications table 3 (avdd = 1.8 v, drvdd = 1.8 v, t min = C40c, t max = +85c, dcs enabled unless otherwise noted.) ad9211-170/-200 ad9211-250 parameter temp min typ max min typ max unit clock inputs differential input voltage 1 full tbd tbd v common-mode voltage 2 full tbd tbd v input resistance full tbd tbd k input capacitance 25c 4 4 pf logic inputs logic 1 voltage full .8 x vdd 2.0 v logic 0 voltage full .2 x avdd 0.8 v logic 1 input current full 10 10 a logic 0 input current full 10 10 a input capacitance 25c 4 4 pf logic outputs 3 v od differential output voltage full 247 454 247 454 mv v os output offset voltage full 1.125 1.375 1.125 1.375 v output coding twos complement, or binary twos complement, or binary 1 all ac specifications tested by driving clk+ and clkC differentially, |(cl k+)C (clkC)| > 200 mv. 2 clock inputs common mode can be externally set, such that xx.xv < (c lk+ or clk- ) < zzz v. 3 lvds r termination = 100 ?
ad9211 preliminary technical data rev. pra | page 6 of 21 switching specifications table 4. (avdd = 1.8 v, drvdd = 1.8 v, t min = C40c, t max = +85c, dcs enabled unless otherwise noted.) ad9211-170/-200 ad9211-250 parameter (conditions) temp min typ max min typ max unit maximum conversion rate 1 full 170/200 250 msps minimum conversion rate 1 full 40 40 msps clk+ pulsewidth high (t eh ) 1 full tbd tbd ns clk+ pulsewidth low (t el ) 1 full tbd tbd ns output (lvds) valid time (t v ) full tbd tbd ns propagation delay (t pd ) full 3.9 3.9 ns rise time (t r ) (20% to 80%) 25c 0.4 0.4 ns fall time (t f ) (20% to 80%) 25c 0.4 0.4 ns dco propagation delay (t cpd ) full 3.2 3.2 ns data to dco skew (t pd C t cpd ) full tbd tbd ns latency (l) full 5 5 cycles aperture delay (t a ) 25c tbd tbd ns aperture uncertainty (jitter, t j ) 25c 0.2 0.2 ps rms out of range recovery time 25c tbd tbd cycles 1 all ac specifications tested by driving clk+ and clkC differentially. n?1 n n+1 n+l n+l+1 n+l+2 n+l+3 t eh t el 1/f s t a n?l t pd l cycles t v n-l+1 n n+1 n+2 t cpd clk+ clk? data out dco? dco+ ain figure 2. timing diagram (l=5 cycles)
preliminary technical data ad9211 rev. pra | page 7 of 21 absolute maximum ratings 1 parameter rating avdd 2.0 v drvdd 2.0v analog inputs C0.5 v to avdd + 0.5 v digital inputs C0.5 v to drvdd + 0.5 v refin inputs C0.5 v to avdd + 0.5 v digital output current 20 ma operating temperature C40oc to +125c storage temperature C65oc to +150c maximum junction temperature 150c maximum case temperature 150c ja 2 tbdc/w 1stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 typical ja = tbd c/w (heat slug soldered) for multilayer board in still air with solid ground plane. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9211 preliminary technical data rev. pra | page 8 of 21 pin configurations and function descriptions ad9211 56 lead for lf-csp top view (not to scale) avdd dnc 48 46 55 54 53 52 47 51 50 56 45 49 44 43 d0+ d0- dnc dnc dco+ dco- drgnd drvdd avdd clk- clk+ avdd dnc avdd avdd cml avdd avdd avdd vin- vin+ avdd avdd rbias avdd 34 32 41 40 39 38 33 37 36 42 31 35 30 29 pdn 25 d7- d8- d8+ d9- (msb) d9+ ovr- ovr+ drgnd drvdd 27 18 19 20 21 26 22 23 16 17 28 24 15 sdio csb reset d7+ sclk 11 d1- d2- d2+ d3- d3+ drvdd drgnd d4- 13 4 5 6 7 12 8 9 2 3 14 10 1 d4+ d5- d5+ d6- d6+ d1+ pin 0 (exposed paddle) = agnd figure 3. pinout table 5. pin function descriptions pin number mnemonic description 30,32,33,34,37,38,39,41, 42,43,46 avdd 1.8 v analog supply. 7, 24,47 drvdd 1.8 v digital output supply. 0 agnd 1 analog ground. 8, 23,48 drgnd 1 digital output ground. 35 vin+ analog inputtrue. 36 vinC analog inputcomplement. 40 cml analog input common mode output pin 44 clk+ clock inputtrue. 45 clkC clock inputcomplement. 31 rbias set pin for chip bias current. (place 1% x kohm resistor terminated to ground). 28 reset chip reset ( active high) 25 sdio serial port input/output pin 26 sclk serial port clock 27 29 csb pwdn serial port chip select (active low) chip power down 49 dcoC data clock outputcomplement. 50 dco+ data clock outputtrue. 51-54 dnc do not connect 55 d0C d0 complement output bit. 56 d0+ d0 true output bit. 1 agnd and drgnd should be tied to a common quiet ground plane.
preliminary technical data ad9211 rev. pra | page 9 of 21 pin number mnemonic description 1 d1C d1 complement output bit. 2 d1+ d1 true output bit. 3 d2C d2 complement output bit. 4 d2+ d2 true output bit. 5 d3C d3 complement output bit. 5 d3+ d3 true output bit. 9 d4C d4 complement output bit. 10 d4+ d4 true output bit. 11 d5C d5 complement output bit. 12 d5+ d5 true output bit. 13 d6C d6 complement output bit. 14 d6+ d6 true output bit. 15 d7C d7 complement output bit. 16 d7+ d7 true output bit. 17 d8C d8 complement output bit. 18 d8+ d8 true output bit. 19 d9C d9 complement output bit. 20 d9+ d9 true output bit. 21 otrC overrange complement output bit. 22 otr+ overrange true output bit.
ad9211 preliminary technical data rev. pra | page 10 of 21 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. crosstalk coupling onto one channel being driven by a low level (C40 dbfs) signal when the adjacent interfering channel is driven by a fullscale signal. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 and again taking the peak measurement. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) calculated from the measured snr based on the equation 02 . 6 76 . 1 db snr enob measured ? = clock pulsewidth/duty cycle pulsewidth high is the minimum amount of time the encode pulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time the clock pulse should be left in low state. at a given clock rate, these specifications define an acceptable clock duty cycle. full-scale input power expressed in dbm. computed using the following equation: ? ? ? ? ? ? ? ? ? ? ? ? = 001 . 0 log 10 2 input rms fullscale fullscale z v power gain error the difference between the measured and ideal full-scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of clk+ and clkC and the time when all output data bits are within valid logic levels. noise (for any range within the adc) calculated as follows: ? ? ? ? ? ? ? ? = 10 10 001 . 0 dbfs dbc dbm noise signal snr fs z v where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the value of the particular input level, and signal is the signal level within the adc
preliminary technical data ad9211 rev. pra | page 11 of 21 reported in db below full scale. this value includes both thermal and quantization noise. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. transient resp onse time the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
ad9211 preliminary technical data rev. pra | page 12 of 21 equivalent circuits vcm 10k 10k avdd avdd clk+ avdd clk- avdd figure 4 clock inputs vin+ vin- avdd 1000 buf buf buf 1000 avdd avdd figure 5. analog inputs (vx=~ 1.3v) avdd in avdd figure 6. logic inputs v+ v+ dataout+ drvdd dataout- v? v? figure 7. data outputs (lvds mode) .
preliminary technical data ad9211 rev. pra | page 13 of 21 typical performance characteristics tbd
ad9211 preliminary technical data rev. pra | page 14 of 21 theory of operation the ad9211 architecture consists of a front-end sample and hold amplifier (sha) followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be ac- or dc-coupled in differential or single-ended modes. the output- staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. analog input and voltage reference the analog input to the ad9211 is a differential buffer. for best dynamic performance, the source impedances driving vin+ and vin C should be matched such that common mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single-ended signal. a wideband transformer, such as mini-circuits adt1-1wt, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.3 v. an internal differential voltage reference creates positive and negative reference voltages that define the 1.25vp-p fixed span of the adc core. this internal voltage reference can be adjusted by means of spi control. see spi control section for more details. differential input configurations optimum performance is achieved while driving the ad9211 in a differential input configuration. for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set to avdd/2+0.5v, and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. figure 8. differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the ad9211. this is especially true in if under-sampling applications where frequencies in the 70 mhz to 100 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. figure 9. differential transformercoupled configuration single-ended input configuration a single-ended input can provide adequate performance in cost-sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. figure 10 details a typical single-ended input configuration. ad9211 vin+ vin ? 33 33 10pf 49.9 0.1 f 1.25v p-p 05491-005 ad9211 vin+ vin ? cml av dd 1v p-p 49.9 523 0.1 f 33 33 20pf 499 499 499 ad8138 05491-004
preliminary technical data ad9211 rev. pra | page 15 of 21 figure 10. single-ended input configuration using spi enabled cml function clock input considerations for optimum performance, the ad9211 the sample clock inputs (clk+ and clk-) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ and clk- pins via a transformer or capacitors. these pins are biased internally and require no additional bias (see figure x). 1.2v clk+ clk- 2pf 2pf avdd figure .equivalent clock input circuit figure x shows one preferred method for clocking the ad9211. the clock source (low jitter) is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad9211 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9211 while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance. clock source clk+ clk- ad9230 figure x. transformer coupled differential clock for ad9230/ad9211 if a low jitter clock is available, another option is to ac-couple a differential pecl signal to the sample clock input pins as shown in figure x. the ad9512 (or same family) from offers excellent jitter performance. clk+ clk- ad9230 0.1uf 0.1uf ad9512 pecl 150 150 figure x. differential pecl sample clock for ad9230/ad9211 1.25vp-p r 4 9 . 9 0 . 1 f 1 0 f 0.1uf a d 9 211 vin+ vin- av dd agnd cml
ad9211 preliminary technical data rev. pra | page 16 of 21 clock input considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9211 contains a dcs (duty cycle stabilizer) that retimes the non-sampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9211. noise and distortion performance are nearly flat for a wide range duty cycles with the dcs on. the duty cycle stabilizer uses a delay-locked loop (dll) to create the non-sampling edge. as a result, any changes to the sampling frequency require approximately tbd clock cycles to allow the dll to acquire and lock to the new rate. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f input ) due only to aperture jitter (t j ) can be calculated by ? ? ? ? ? ? = j input t f 2 20 log snr in the equation, the rms aperture jitter represents the root- mean square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. if under-sampling applications are particularly sensitive to jitter, see figure 11. input frequency (mhz) 1 40 75 70 65 60 55 50 45 1000 100 10 0.2ps 0.5ps 1.0ps 1.5ps 2.0ps 2.5ps 3.0ps snr (dbc) figure 11. snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9211. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. power dissipation and power down mode as shown in figure 12 and figure 14, the power dissipated by the ad9211 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. figure 12. ad9211-170, supply current vs. f sample for f in = 10.3 mhz figure 13. ad9211-200, supply current vs. f sample for f in = 10.3 mhz
preliminary technical data ad9211 rev. pra | page 17 of 21 figure 14. ad9211-250, supply current vs. f sample for f in = 10.3 mhz by asserting the pdwn pin high, the ad9211 is placed in standby mode. in this state, the adc typically dissipates 1 mw even if the clk and analog inputs are static. during standby, the output drivers are placed in a high impedance state. reasserting the pdwn pin low returns the ad9211 into its normal operational mode. an additional stand by mode is supported by means of varying the clock input. when the clock rate falls below 20mhz, the ad9211 will assume a standby state. in this case, the biasing network and internal reference remain on but digital circuitry is powered down. upon reactivating the clock, the ad9211 will resume normal operation after allowing for the pipeline latency. digital outputs the ad9228s differential outputs conform to the ansi-644 lvds standard on default power up. the lvds driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9211s lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capa- bility for superior switching performance in noisy environ- ments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. it is recommended to keep the trace length no longer than 12 inches and to keep differential output traces close together and at equal lengths. the format of the output data is offset binary. an example of the output coding format can be found in table 7. table 7. digital output coding code (vin+) ? (vin?), input span = 1.252 v p-p (v) digital output offset binary (d9 ... d0) 1024 1.000 11 1111 1111 512 0 10 0000 0000 511 ?0.000488 01 1111 1111 0 ?1.00 00 0000 0000 as detailed in interfacing to adc spi , the data format can be selected for either offset binary or twos complement, or gray code (spi access only). out-of-range (otr) an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. otr is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. thus, otr has the same pipeline latency as the digital data. otr is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in figure 15. otr will remain high until the analog input returns to within the input range and another conversion is completed. by logically and-ing otr with the msb and its complement, over-range high or under-range low conditions can be detected. figure 15. otr relation to input voltage and output data for ad9230/ad9211 timing the ad9211 provides latched data outputs with a pipeline delay of five clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal.
ad9211 preliminary technical data rev. pra | page 18 of 21 the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9211. these transients can degrade the converters dynamic performance. the ad9211 also provides data clock output (dco) intended for capturing the data in an external register. the data outputs are valid on the rising edge of dco. the lowest typical conversion rate of the ad9211 is 40 msps. at clock rates below 1 msps, the ad9211 will assume standby mode. rbias the ad9211 requires the user to place a 10k resistor between the rbias pin and ground. this resister should have a 1% tolerance, and is used to set the master current reference of the adc core. ad9211 configuration using the spi the ad9211 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space inside the adc. this gives the user added flexibility to customize device operation depending on the application. addresses are accessed (programmed or read back) serially in one-byte words. each byte may be further divided down into fields which are documented in the memory map section below. there are three pins that define the serial port interface or spi to this particular adc. they are the spi sclk / dfs, spi sdio / dcs, and csb pins. the sclk/dfs (serial clock) is used to synchronize the read and write data presented the adc.. the sdio / dcs (serial data input/output) is a dual purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb or chip select bar is an active low control that enables or disables the read and write cycles. see table x. table x. serial port pins pin function sclk sclk (serial clock) is the serial shift clock in. sclk is used to synchronize serial interface reads and writes. sdio sdio (serial data input/output) is a dual purpose pin. the typical role for this pi n is an input and output depending on the instruction being sent and the relative position in the timing frame. csb reset csb (chip select bar) is active low controls that gates the read and write cycles. master device reset. when asserted, device assumes default settings. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing. an example of the serial timing and its definitions can be found in figure x and table x. table x. spi timing diagram specifications spec name meaning t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock t s setup time between csb and sclk t h hold time between csb and sclk t hi minimum period that sclk should be in a logic high state t lo minimum period that sclk should be in a logic low state during an instruction phase a 16bit instruction is transmitted. data then follows the instruction phase and is determined by the w0 and w1 bits which is 1 or more bytes of data. all data is composed of 8bit words. the first bit of each individual byte of serial data indicates whether this is a read or write command. this allows the serial data input/output (sdio) pin to change direction from an input to an output. data may be sent in msb or in lsb first mode. msb first is default on power up and may be changed by changing the configuration register. for more information about this feature and others see spi doc at www.analog.com.
preliminary technical data ad9211 rev. pra | page 19 of 21 hardware interface the pins described in table x comprise the physical interface between the users programming device and the serial port of the ad9211. all serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value 10 k). this interface is flexible enough to be controlled by either proms or pic mirocontrollers as well. this provides the user to use an alternate method to program the adc other than a spi controller. if the user chooses to not use the spi interface, some pins serve a dual function and are associated with a specific function when strapped externally to avdd or ground during device power on. the section below describes the strappable functions supported on the ad9211. ad9211 configuration without the spi in applications that do not interface to the spi control registers, the spi sdio / dcs and spi sclk / dfs pins can alternately serve as stand alone cmos compatible control pins when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. in this mode the spi csb chip select should be connected to avdd, which will disable the serial port interface. table 6. mode selection pin external voltage configuration avdd duty cycle stabilizer enabled spi sdio / dcs agnd duty cycle stabilizer disabled avdd 2s complement enabled spi sclk / dfs agnd offset binary enabled reading the memory map table each row in the memory map table has eight address locations. the memory map is roughly divided into four sections: chip configuration register map (address 0x00 to address 0x02), device index and transfer register map (address 0x04 to address 0x05, and address 0xff), global adc function register map (address 0x08 to address 0x09), and flexible adc functions register map (address 0x0b to address 0x25). the flexible adc functions register map is product specific. starting from the right hand column, the memory map register in table x documents the default hex value for each hex address shown. the column with the heading byte 7 (msb) is the start of the default hex value giving. for example, hex address 0x14, flex_output_phase has a hex default value of 00h. this means bit 3 = 0, bit 2 = 0, bit 1 = 1, and bit 0 = 1 or 0011 in binary. this setting is the default output clock or dco phase adjust option. the default value adjusts the dco phase 90deg relative to the nominal dco edge and 180deg relative to the data edge. for more information on this function and others consult the spi doc at www.analog.com. open locations all locations marked as open are currently not supported for this particular device. when required, these locations should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x14). if the whole address location is open (for example, address 0x13), then this address location does not need to be written. default values coming out of reset, some of the address locations (but not all) are loaded with default values. the default values for the registers are given in the table x. logic levels an explanation of various registers, bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. figure x. serial port interface timing diagram
ad9211 preliminary technical data rev. pra | page 20 of 21 table x. ad9211 device configuration register memory map .
preliminary technical data ad9211 rev. pra | page 21 of 21 outline dimensions compliant to jedec standards mo-220-vlld-2 a 56-lead lead frame chip scale package [lfcsp_vq] 8 x 8 mm body, very thin quad (cp-56-2) dimensions shown in millimeters 112805-0 pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 4.45 4.30 sq 4.15 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.30 min exposed pad (bottom view) figure 16. mechanical drawing (subject to change) ordering guide model temperature range package description package option AD9211BCPZ-170 1 ?40c to +85c 56-lead lead frame chip scale package (lfcsp-vq) cp-56 ad9211bcpz-200 1 ?40c to +85c 56-lead lead frame chip scale package (lfcsp-vq) cp-56 ad9211bcpz-250 1 ?40c to +85c 56-lead lead frame chip scale package (lfcsp-vq) cp-56 ad9211-250eb 25c lvds evaluation board with ad9211bcpz-250 ad9211-200eb 25c lvds evaluation board with ad9211bcpz-200 ad9211-170eb 25c lvds evaluation board with AD9211BCPZ-170 1 z=pb-free part ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective companies. printed in the u.s.a. pr06041-0-3/06(pra)

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